1. Field of the Invention
The present invention relates to a method of manufacturing a field effect transistor (FET) and, more specifically, to a method of manufacturing an FET, in which transistors having respectively different threshold voltages are simultaneously manufactured on a single substrate through a lithography process using a multilayered resist layer and a dry etching process using an etch selectivity of the resist layer with respect to an insulating layer. In this method, the transistors having respectively different threshold voltages can be manufactured without any additional mask pattern, thus reducing the number of processes to be performed and the cost of production.
2. Discussion of Related Art
In general, semiconductor devices, such as a high electron mobility transistor (HEMT) using a compound semiconductor and a metal semiconductor field effect transistor (MESFET), have been manufactured using an ohmic metal layer, which is obtained by sequentially depositing an AuGe layer, a Ni layer, and an Au layer to a predetermined thickness.
In the manufacture of these semiconductor devices, such as the HEMT using the compound semiconductor and the MESFET, a gate recess process, which is the most important process, is typically performed by measuring currents and includes at least one of a dry process, a wet process, and a combination thereof.
The gate recess process is performed using BCl3 gas or SF6 gas in a dry etching system, such as an electron cyclotron resonance (ECR) system or an inductive coupled plasma (ICP) system. Also, the gate recess process may be carried out using a variety of wet etchants, for example, an H3PO4-based solution with a mixture of H3PO4, H2O2, and H2O in an appropriate ratio.
Further, the manufacture of the semiconductor devices, such as the HEMT using the compound semiconductor and the MESFET, includes forming a gate electrode by sequentially depositing, for example, a Ti layer, a Pt layer, and an Au layer, to a predetermined thickness.
In the above-described conventional manufacture of the semiconductor devices, when transistors having respectively different threshold voltages are simultaneously formed on a single substrate, separate mask patterns are required. Thus, subsequent processes including a gate recess process should be separately performed.
For example, given a HEMT device using a compound semiconductor substrate (e.g., a GaAs substrate, an InP substrate, or a GaN substrate), the manufacture of an enhancement mode FET (E-FET) and a depletion mode FET (D-FET) on the same substrate at the same time requires not only separately performing lithography processes using masks or electron-beam (e-beam) lithography processes, but also separately performing subsequent gate recess processes, so that gate recess regions having respectively different etching depths can be obtained.
Accordingly, when the E-FET and the D-FET are manufactured on the same substrate at the same time, the conventional method leads to an increase in the cost of production with a great number of processes and a drop in productivity.